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encore? iii full speed usb controll er cy7c6421 5 cypress semiconductor corporation 198 champion court san jose , ca 95134-1709 408-943-2600 document 38-08036 rev. *a revised september 26, 2005 1.0 features powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? two 8x8 multiply, 32-bit accumulate ? 3.0 to 5.25v operating voltage ? usb temperature range: 0c to +70c advanced peripherals (encore? iii blocks) ? analog encore iii block provides: up to 14-bit adcs ? 4 digital encore iii blocks provide: 8-bit pwms full-duplex uart multiple spi masters or slaves connectable to all gpio pins complex peripherals by combining blocks full-speed usb (12 mbps) ? four unidirectional endpoints ? one bidirectional control endpoint ? usb 2.0 compliant ? dedicated 256 byte buffer ? no external crystal required flexible on-chip memory ? 16k flash program storage 50,000 erase/write cycles ? 1k sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25-ma sink on all gpio ? pull-up, pull-down, high- z, strong, or open drain drive modes on all gpio ? configurable interrupt on all gpio precision, programmable clocking ? internal 4% 24-/48-mhz oscillator ? internal oscillator for watchdog and sleep ? 0.25% accuracy for usb with no external components additional system resources ?i 2 c ? slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc? designer) ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k bytes trace memory encore iii core figure 1-1. encore iii block diagram
cy7c6421 5 document 38-08036 rev. *a page 2 of 26 2.0 applications pc hid devices ? mice (optomechanical, optical, trackball) ? keyboards ? joysticks gaming ? game pads ? console keyboards general purpose ? barcode scanners ?pos terminal ? consumer electronics ?toys ? remote controls ? usb to serial 3.0 encore iii functional overview encore iii is based on the flexible psoc architecture and is a full-featured, full-speed (12 mbps) usb part. configurable analog, digital, and interconnect circuitry enable a high level of integration in a host of consumer, and communication applica- tions. this architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable io are included in both 28-pin ssop and 56-pin qfn packages. the encore iii architecture, as illustrated in figure 1-1 , is comprised of four main areas: encore iii core, digital system, analog system, and system resources including a full-speed usb port. configurable global busing allows all the device resources to be combined into a complete custom system. the encore iii cy7c64215 can have up to seven io ports that connect to the global digital and analog intercon- nects, providing access to 4 digital blocks and 1 analog block. 3.1 encore iii core the encore iii core is a powerful engine that supports a rich feature set. the core includes a cpu, memory, clocks, and configurable gpio (general purpose io). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard architecture microprocessor. the cpu utilizes an interrupt controller with up to 20 vectors, to simplify programming of real-time embedded events. program execution is timed and protected using the included sleep and watch dog timers (wdt). memory encompasses 16k of flash for program storage, 1k of sram for data storage, and up to 2k of eeprom emulated using the flash. program flash utilizes four protection levels on blocks of 64 bytes, allowing customized software ip protection. encore iii incorporates flexible internal clock generators, including a 24-mhz imo (internal main oscillator) accurate to 8% over temperature and voltage. the 24-mhz imo can also be doubled to 48 mhz for use by the digital system. a low- power 32 khz ilo (internal low-speed oscillator) is provided for the sleep timer and wdt. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the encore iii. in usb systems, the imo will self-tune to 0.25% accuracy for usb communication. encore iii gpios provide connection to the cpu, digital and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external interfacing. every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. 3.2 the digital system the digital system is composed of 4 digital encore iii blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. digital peripheral configurations include those listed below. full-speed usb (12 mbps) pwms (8-bit) uart 8-bit with selectable parity spi master and slave i2c slave and multi-master the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. 3.3 the analog system the analog system is composed of 1 configurable block, comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital encore iii block array to a nalog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 1 port 0 port 3 port 2 port 5 port 4 port 7 figure 3-1. digital system block diagram
cy7c6421 5 document 38-08036 rev. *a page 3 of 26 flexible and can be customized to support specific application requirements. encore iii analog function supports the analog-to-digital converters (up to 2, with 6- to 14-bit resolution, selectable as incremental, delta sigma, and sar) analog blocks are arranged in a column of three, which includes one ct (continuous time - ac b00 or ac b01) and two sc (switched capacitor - asc10 and asd20 or asd11 and asc21) blocks, as shown in figure 3-2 . 3.3.1 the analog multiplexer system the analog mux bus can connect to every gpio pin in ports 0?5. pins can be connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with comparators and analog-to-digital converters. it can be split into two sections for simultaneous dual-channel processing. an additional 8:1 analog input multiplexer provides a second path to bring port 0 pins to the analog array. 3.4 additional system resources system resources provide additional capability useful to complete systems. additional resources include a multiplier, decimator, low voltage detection, and power-on reset. brief statements describing the merits of each resource follow. full-speed usb (12 mbps) with 5 configurable endpoints and 256 bytes of ram. no external components required except two series resistors. wider than commercial temper- ature usb operation (?10c to +85c). two multiply accumulates (macs) provide fast 8-bit multi- pliers with 32-bit accumulate, to assist in both general math as well as digital filters. the decimator provides a custom hardware filter for digital signal processing applications including the creation of del- ta sigma adcs. digital clock dividers provide three customizable clock fre- quencies for use in applications. the clocks can be routed to both the digital and analog systems. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the ap- plication of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. hapi interface for a 8-bit bus width to accommodate data transfer with an external microcontroller or similar device. 3.5 encore iii device characteristics encore iii devices have 4 digital blocks and 6 analog blocks. the following table lists the resources available for specific encore iii device. 4.0 getting started the quickest path to understanding encore iii silicon is by reading this data sheet and using the psoc designer integrated development environment (ide). this data sheet is an overview of the encore iii integrated circuit and presents specific pin, register, and electrical specifications. encore iii is based on the architecture of the cy8c24794. for in-depth information, along with detailed programming information, reference the psoc? mixed-signal array technical reference manual . for up-to-date ordering, packaging, and electrical specifi- cation information, reference the latest encore iii device data sheets on the web at http://www.cypress.com . 4.1 development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store acb00 acb01 block ar r a y array input configuration a c i1[1:0] asd20 a c i0[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address b us, d ata b us, etc.) analog reference all io (excep t port 7) analog mux bus figure 3-2. analog system block diagram table 3-1. encore iii device characteristics part number digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy7c64215 -28pvxc up to 22 1 4 22 2 2 6 1k 16k cy7c64215 -56lfxc up to 50 1 4 48 2 2 6 1k 16k
cy7c6421 5 document 38-08036 rev. *a page 4 of 26 contains development kits, c compilers, and all accessories for encore iii development. go to the cypress online store web site at http://www.cypress.com, click the online store shopping cart icon at the bottom of the web page, and click usb (universal serial bus) to view a current list of available items. 5.0 development tools psoc designer is a microsoft ? windows ? -based, integrated development environment for the encore iii. the psoc designer ide and application runs on windows nt 4.0, windows 2000, windows millennium (me), or windows xp. (refer to the psoc designer functional flow diagram below.) psoc designer helps the customer to select an operating configuration for the encore iii, write application code that uses the encore iii, and debug the application. this system provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high-level c language compiler developed specifically for the devices in the family. 5.1 psoc designer software subsystems 5.1.1 device editor the device editor subsystem allows the user to select different onboard analog and digital components called user modules using the encore iii blocks. examples of user modules are adcs, spim, uart, and pwms. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic config- uration allows for changing configurations at run time. psoc designer sets up power-on initialization tables for selected encore iii block configurations and creates source code for an application framework. the framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of encore iii block configurations at run time. psoc designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the device data sheet. once the framework is generated, the user can add application-specific code to flesh out the framework. it?s also possible to change the selected components and regen- erate the framework. 5.1.2 application editor in the application editor you can edit your c language and assembly language source code. you can also assemble, compile, link, and build. assembler. the macro assembler allows the assembly code to be merged seamlessly with c code. the link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler. a c language compiler is available that supports the encore iii family of devices. even if you have never worked in the c language before, the product quickly allows you to create complete c programs for the encore iii devices. the embedded, optimizing c compiler provides all the features of c tailored to the encore iii architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. 5.1.3 debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the encore iii device. debugger commands allow the designer to read and program and read and write data memory, read and write io registers, read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. 5.1.4 online help system the online help system displays online, context-sensitive help for the user. designed for procedural and quick reference, commands results psoc t m designer core engine pso c conf iguration sheet manufacturing inf ormation file device database importable de s i g n database device programmer graphical designer interface context sensitive hel p emulation po d in-circuit emulator project database application database us e r modules library psoc tm designer figure 5-1. psoc designer subsystems
cy7c6421 5 document 38-08036 rev. *a page 5 of 26 each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. 5.2 hardware tools 5.2.1 in-circuit emulator a low-cost, high-functionality ice cube is available for devel- opment support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and will operate with all encore iii devices. 6.0 designing with user modules the development process for the encore iii device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the encore iii architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. these configurable resources, called encore iii blocks, have the ability to implement a wide variety of user-selectable functions. each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the io pins. iterative development cycles permit you to adapt the hardware as well as the software. this substantially lowers the risk of having to select a different part to meet the final design requirements. to speed the development process, the psoc designer integrated development environment (ide) provides a library of pre-built, pre-tested hardware peripheral functions, called ?user modules.? user modules make selecting and imple- menting peripheral devices simple, and come in analog, digital, and mixed signal varieties. the user module library contains 8 peripherals: adcinc, pwm8, uart, spim, spis, lcd, i2chw, i2cm and usbfs. each user module establishes the basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pulse width modulator user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit the designer to establish the pulse width and duty cycle. user modules also provide tested software to cut development time. the user module application programming interface (api) provides high-level functions to control and respond to hardware events at run-time. the api also provides optional interrupt service routines that can be adapted as needed. the api functions are documented in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specifications. each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. you pick the user modules you need for your project and map them onto the psoc blocks with point-and-click simplicity. next, you build signal chains by interconnecting user modules to each other and the io pins. at this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate application? step. this causes psoc designer to generate source code that automat- ically configures the device to your specification and provides the high-level user module api functions. the next step is to write your main program, and any sub- routines using psoc designer?s application editor subsystem. the application editor includes a project manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a professional-strength ?makefile? system to automatically analyze all file dependencies and run the compiler and assembler as necessary. project-level options control optimization strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. debugger interf ace to ice application editor device editor pr o je c t manager source code ed it o r storage inspector us er module selection placement and pa r a me t e r -ization generate application build al l event & breakpoint manager build manager source code generator figure 6-1. user module and source code developmen t flows
cy7c6421 5 document 38-08036 rev. *a page 6 of 26 the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the in-circuit emulator (ice cube) where it runs at full speed. debugger capabilities rival those of systems costing many times more. in addition to tradi- tional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. 7.0 document conventions 7.1 acronyms used the following table lists the acronyms that are used in this document. 7.2 units of measure a units of measure table is located in the electrical specifica- tions section. table 11-1 on page 11 lists all the abbreviations used to measure the encore iii devices. 7.3 numeric naming hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexidecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (e.g., 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimal. acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc programmable system-on-chip? pwm pulse width modulator sc switched capacitor sram static random access memory acronym description
cy7c6421 5 document 38-08036 rev. *a page 7 of 26 8.0 56-pin part pinout the cy7c64215 encore iii device is available in a 56-pin package which is listed and illustrated in the following table. every port pin (labeled with a ?p?) is capable of digital io. however, vss and vdd are not capable of digital io. table 8-1. 56-pin part pinout (mlf * ) pin no. type name description cy7c64215 56-pin encore iii device digital analog 1 io i, m p2[3] direct switched capacitor block input. 2 io i, m p2[1] direct switched capacitor block input. 3 io m p4[7] 4 io m p4[5] 5 io m p4[3] 6 io m p4[1] 7 io m p3[7] 8 io m p3[5] 9 io m p3[3] 10 io m p3[1] 11 io m p5[7] 12 io m p5[5] 13 io m p5[3] 14 io m p5[1] 15 io m p1[7] i2c serial clock (scl). 16 io m p1[5] i2c serial data (sda). 17 io m p1[3] 18 io m p1[1] i2c serial clock (scl), issp-sclk. 19 power vss ground connection. 20 usb d+ 21 usb d- 22 power vdd supply voltage. 23 io p7[7] 24 io p7[0] 25 io m p1[0] i2c serial data (sda), issp-sdata. 26 io m p1[2] 27 io m p1[4] 28 io m p1[6] 29 io m p5[0] pin no. type name description 30 io m p5[2] digital analog 31 io m p5[4] 44 io m p2[6] external voltage reference (vref) input. 32 io m p5[6] 45 io i, m p0[0] analog column mux input. 33 io m p3[0] 46 io i, m p0[2] analog column mux input and column output. 34 io m p3[2] 47 io i, m p0[4] analog column mux input and column output. 35 io m p3[4] 48 io i, m p0[6] analog column mux input. 36 io m p3[6] 49 power vdd supply voltage. 37 io m p4[0] 50 power vss ground connection. 38 io m p4[2] 51 io i, m p0[7] analog column mux input, integration input #1. 39 io m p4[4] 52 io io, m p0[5] analog column mux input and column output, integration input #2. 40 io m p4[6] 53 io io, m p0[3] analog column mux input and column output. 41 io i, m p2[0] direct switched capacitor block input. 54 io i, m p0[1] analog column mux input. 42 io i, m p2[2] direct switched capacitor block input. 55 io m p2[7] 43 io m p2[4] external analog ground (agnd) in- put. 56 io m p2[5] legend a = analog, i = input, o = output, and m = analog mux input. * the mlf package has a center pad that must be connected to ground (vss). mlf (top view) a, i, m, p2[3] a, i, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[7] m, p5[5] m, p5[3] m, p5[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 m , i2c scl, p1[7] m , i2c sda, p1[5] m, p1[3] m , i2c scl, p1[1] vss d+ d- vdd p7[7] p7[0] m, i2c sda, p1[0] m, p1[2] m, p1[4] m, p1[6] 15 16 17 18 19 20 21 22 23 24 25 26 27 28 p2[4], m p2[6], m p0[0], a, i, m p0[2], a, i, m p0[4], a, i, m p0[6], a, i, m vdd vss p0[7], a, i, m p0[5], a, io, m p0[3], a, io, m p0[1], a, i, m p2[7], m p2[5], m 43 44 45 46 47 48 49 50 51 52 53 54 55 56 p2[2], a, i, m p2[0], a, i, m p4[6], m p4[4], m p4[2], m p4[0], m p3[6], m p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m 42 41 40 39 38 37 36 35 34 33 32 31 30 29
cy7c6421 5 document 38-08036 rev. *a page 8 of 26 9.0 28-pin part pinout the cy7c64215 encore iii device is available in a 28-pin package which is listed and illustrated in the following table. every port pin (labeled with a ?p?) is capable of digital io. however, vss and vdd are not capable of digital io. 10.0 register reference 10.1 register conventions 10.1.1 abbreviations used the register conventions specific to this section are listed in the following table. 10.2 register mapping tables the encore iii device has a total register address space of 512 bytes. the register space is referred to as io space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. table 9-1. 28-pin part pinout (ssop) pin no. type name description cy7c64215 28-pin encore iii device digital analog 1 power gnd ground connection 2 io i, m p0[7] analog column mux input, integration in- put #1. 3 io io,m p0[5] analog column mux input and column output, integration input #2. 4 io io,m p0[3] analog column mux input and column output. 5 io i,m p0[1] analog column mux input. 6 io mp2[5] 7 io m p2[3] direct switched capacitor block input. 8 io m p2[1] direct switched capacitor block input. 9 io m p1[7] i2c serial clock (scl). 10 io m p1[5] i2c serial data (sda). 11 io m p1[3] 12 io m p1[1] i2c serial clock (scl), issp-sclk. 13 power gnd ground connection 14 usb d+ 15 usb d-] 16 power vdd supply voltage. 17 io m p1[0] i2c serial data (sda), issp-sdata. 18 io mp1[2] 19 io m p1[4] 20 io m p1[6] 21 io m p2[0] direct switched capacitor block input. 22 io m p2[2] direct switched capacitor block input. 23 io m p2[4] external analog ground (agnd) input. 24 io m p0[0] analog column mux input. 25 io m p0[2] analog column mux input and column output. 26 io m p0[4] analog column mux input and column output. 27 io m p0[6] analog column mux input. 28 power vdd] supply voltage. legend a = analog, i = input, o = output, and m = analog mux input. * the mlf package has a center pad that must be connected to ground (vss). ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vdd p0[6], ai p0[4], ai p0[2], ai p0[0], ai p2[ 4] p2[2], ai p2[0], ai p1[ 6] p1[ 4] p1[ 2] p1[0], i2c sda vdd d - vss ai, p0[7] ai o, p0[5] ai o, p0[3] ai, p0[1] p2[5] ai, p2[3] ai , p2 [ 1] i2c scl, p1[ 7] i2c sda, p1[5] p1[3] i2c scl, p1[1] vss d + convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
cy7c6421 5 document 38-08036 rev. *a page 9 of 26 10.3 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw pma0_dr 40 rw asc10cr0 80 rw c0 prt0ie 01 rw pma1_dr 41 rw asc10cr1 81 rw c1 prt0gs 02 rw pma2_dr 42 rw asc10cr2 82 rw c2 prt0dm2 03 rw pma3_dr 43 rw asc10cr3 83 rw c3 prt1dr 04 rw pma4_dr 44 rw asd11cr0 84 rw c4 prt1ie 05 rw pma5_dr 45 rw asd11cr1 85 rw c5 prt1gs 06 rw pma6_dr 46 rw asd11cr2 86 rw c6 prt1dm2 07 rw pma7_dr 47 rw asd11cr3 87 rw c7 prt2dr 08 rw usb_sof0 48 r 88 c8 prt2ie 09 rw usb_sof1 49 r 89 c9 prt2gs 0a rw usb_cr0 4a rw 8a ca prt2dm2 0b rw usbio_cr0 4b # 8b cb prt3dr 0c rw usbio_cr1 4c rw 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw ep1_cnt1 4e # 8e ce prt3dm2 0f rw ep1_cnt 4f rw 8f cf prt4dr 10 rw ep2_cnt1 50 # asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw ep2_cnt 51 rw asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw ep3_cnt1 52 # asd20cr2 92 rw d2 prt4dm2 13 rw ep3_cnt 53 rw asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw ep4_cnt1 54 # asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw ep4_cnt 55 rw asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw ep0_cr 56 # asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw ep0_cnt 57 # asc21cr3 97 rw i2c_scr d7 # 18 ep0_dr0 58 rw 98 i2c_dr d8 rw 19 ep0_dr1 59 rw 99 i2c_mscr d9 # 1a ep0_dr2 5a rw 9a int_clr0 da rw 1b ep0_dr3 5b rw 9b int_clr1 db rw prt7dr 1c rw ep0_dr4 5c rw 9c int_clr2 dc rw prt7ie 1d rw ep0_dr5 5d rw 9d int_clr3 dd rw prt7gs 1e rw ep0_dr6 5e rw 9e int_msk3 de rw prt7dm2 1f rw ep0_dr7 5f rw 9f int_msk2 df rw dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w amuxcfg 61 rw a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcb02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_d fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
cy7c6421 5 document 38-08036 rev. *a page 10 of 26 10.4 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw pma0_wa 40 rw asc10cr0 80 rw usbio_cr2 c0 rw prt0dm1 01 rw pma1_wa 41 rw asc10cr1 81 rw usb_cr1 c1 # prt0ic0 02 rw pma2_wa 42 rw asc10cr2 82 rw prt0ic1 03 rw pma3_wa 43 rw asc10cr3 83 rw prt1dm0 04 rw pma4_wa 44 rw asd11cr0 84 rw ep1_cr0 c4 # prt1dm1 05 rw pma5_wa 45 rw asd11cr1 85 rw ep2_cr0 c5 # prt1ic0 06 rw pma6_wa 46 rw asd11cr2 86 rw ep3_cr0 c6 # prt1ic1 07 rw pma7_wa 47 rw asd11cr3 87 rw ep4_cr0 c7 # prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf prt4dm0 10 rw pma0_ra 50 rw 90 gdi_o_in d0 rw prt4dm1 11 rw pma1_ra 51 rw asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw pma2_ra 52 rw asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw pma3_ra 53 rw asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw pma4_ra 54 rw asc21cr0 94 rw d4 prt5dm1 15 rw pma5_ra 55 rw asc21cr1 95 rw d5 prt5ic0 16 rw pma6_ra 56 rw asc21cr2 96 rw d6 prt5ic1 17 rw pma7_ra 57 rw asc21cr3 97 rw d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b mux_cr3 db rw prt7dm0 1c rw 5c 9c dc prt7dm1 1d rw 5d 9d osc_go_en dd rw prt7ic0 1e rw 5e 9e osc_cr4 de rw prt7ic1 1f rw 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw cmp_go_en1 65 rw a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac mux_cr4 ec rw dcb03in 2d rw tmp_dr1 6d rw ad mux_cr5 ed rw dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_cr fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
cy7c6421 5 document 38-08036 rev. *a page 11 of 26 11.0 electrical specifications this section presents the dc and ac electrical specifications of the cy7c64215 encore iii. for the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com. specifications are valid for 0c < t a < 70c and t j < 100c, except where noted. specifications for devices running at greater than 12 mhz are valid for 0c < t a < 70c and t j < 82c. the following table lists the units of measure that are used in this section. table 11-1. units of measure symbol unit of measure symbol unit of measure c degree celsius w microwatts db decibels ma milliampere ff femto farad ms millisecond hz hertz mv millivolts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k ? kilohm w ohm mhz megahertz pa picoampere m ? megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts s sigma: one standard deviation vrms microvolts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage v a l i d o p e r a t i n g r e g i o n figure 11-1. voltage versus cpu frequency
cy7c6421 5 document 38-08036 rev. *a page 12 of 26 11.1 absolute maximum ratings 11.2 operating temperature 11.3 dc electrical characteristics 11.3.1 dc chip-level specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 11-2. absolute maximum ratings parameter description min. typ. max. unit notes t stg storage temperature ?55 ? +100 c higher storage temperatures will reduce data retention time. t a ambient temperature with power applied ?40 ? +85 c vdd supply voltage on vdd relative to vss ?0.5 ? +6.0 v v io dc input voltage vss ? 0.5 ? vdd + 0.5 v v io2 dc voltage applied to tri-state vss ? 0.5 ? vdd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma i maio maximum current into any port pin configured as analog driver ?50 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 11-3. operating temperature parameter description min. typ. max. unit notes t a ambient temperature 0 ? +70 c t j junction temperature 0 ? +88 c the temperature rise from ambient to junction is package specific. see ?thermal impedance? on page 24. the user must limit the power consumption to comply with this requirement. table 11-4. dc chip-level specifications parameter description min. typ. max. unit notes vdd supply voltage 3.0 ? 5.25 v see dc por and lvd specifications, table 11-12 on page 16. i dd5 supply current, imo = 24 mhz (5v) ? 14 27 ma conditions are vdd = 5.0v, t a = 25c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. i dd3 supply current, imo = 24 mhz (3.3v) ? 8 14 ma conditions are vdd = 3.3v, t a = 25c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.367 khz, analog power = off. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. [1] ? 3 6.5 a conditions are with internal slow speed oscillator, vdd = 3.3v, 0c < t a < 55c, analog power = off. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. [1] ? 4 25 a conditions are with internal slow speed oscillator, vdd = 3.3v, 55c < t a < 70c, analog power = off. note: 1. standby current includes all functions (por, lvd, wdt, sleep time) needed for reliable system operation. this should be compa red with devices that have similar functions enabled.
cy7c6421 5 document 38-08036 rev. *a page 13 of 26 11.3.2 dc general purpose io specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 11.3.3 dc full-speed usb specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 11-5. dc gpio specifications parameter description min. typ. max. unit notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level vdd ? 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined iol budget. v il input low level ? ? 0.8 v vdd = 3.0 to 5.25. v ih input high level 2.1 ? v vdd = 3.0 to 5.25. v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25c. table 11-6. dc full-speed (12 mbps) usb specifications parameter description min. typ. max. unit notes usb interface v di differential input sensitivity 0.2 ? ? v | (d+) ? (d?) | v cm differential input common mode range 0.8 ? 2.5 v v se single ended receiver threshold 0.8 ? 2.0 v c in transceiver capacitance ? ? 20 pf i io high-z state data line leakage ?10 ? 10 a0v < v in < 3.3v. r ext external usb series resistor 23 ? 25 w in series with each usb pin. v uoh static output high, driven 2.8 ? 3.6 v 15 k ? 5% to ground. internal pull-up enabled. v uohi static output high, idle 2.7 ? 3.6 v 15 k ? 5% to ground. internal pull-up enabled. v uol static output low ? ? 0.3 v 15 k ? 5% to ground. internal pull-up enabled. z o usb driver output impedance 28 ? 44 w including r ext resistor. v crs d+/d? crossover voltage 1.3 ? 2.0 v
cy7c6421 5 document 38-08036 rev. *a page 14 of 26 11.3.4 dc analog output buffer specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 11-7. 5v dc analog output buffer specifications parameter description min. typ. max. unit notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 ? vdd - 1.0 v r outob output resistance power = low power = high ? ? 0.6 0.6 ? ? w w v ohighob high output voltage swing (load = 32 ohms to vdd/2) power = low power = high 0.5 x vdd + 1.1 0.5 x vdd + 1.1 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd ? 1.3 0.5 x vdd ? 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 53 64 ? db (0.5 x vdd ? 1.3) < v out < (vdd ? 2.3). table 11-8. 3.3v dc analog output buffer specifications parameter description min. typ. max. unit notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 - vdd - 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? w w v ohighob high output voltage swing (load = 1k ohms to vdd/2) power = low power = high 0.5 x vdd + 1.0 0.5 x vdd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1k ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd ? 1.0 0.5 x vdd ? 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 34 64 ? db (0.5 x vdd ? 1.0) < v out < (0.5 x vdd + 0.9).
cy7c6421 5 document 38-08036 rev. *a page 15 of 26 11.3.5 dc analog reference specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 11-9. 5v dc analog reference specifications parameter description min. typ. max. unit bg bandgap voltage reference 1.28 1.30 1.32 v ? agnd = vdd/2 [2] vdd/2 ? 0.04 vdd/2 ? 0.01 vdd/2 + 0.007 v ? agnd = 2 x bandgap [2] 2 x bg ? 0.048 2 x bg ? 0.030 2 x bg + 0.024 v ? agnd = p2[4] (p2[4] = vdd/2) [2] p2[4] ? 0.011 p2[4] p2[4] + 0.011 v ? agnd = bandgap [2] bg ? 0.009 bg + 0.008 bg + 0.016 v ? agnd = 1.6 x bandgap [2] 1.6 x bg ? 0.022 1.6 x bg ? 0.010 1.6 x bg + 0.018 v ? agnd block to block variation (agnd = vdd/2) [2] ?0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap vdd/2 + bg ? 0.10 vdd/2 + bg vdd/2 + bg + 0.10 v ? refhi = 3 x bandgap 3 x bg ? 0.06 3 x bg 3 x bg + 0.06 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3v) 2 x bg + p2[6] ? 0.113 2 x bg + p2[6] ? 0.018 2 x bg + p2[6] + 0.077 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) p2[4] + bg ? 0.130 p2[4] + bg ? 0.016 p2[4] + bg + 0.098 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] + p2[6] ? 0.133 p2[4] + p2[6] ? 0.016 p2[4] + p2[6]+ 0.100 v ? refhi = 3.2 x bandgap 3.2 x bg ? 0.112 3.2 x bg 3.2 x bg + 0.076 v ? reflo = vdd/2 ? bandgap vdd/2 ? bg ? 0.04 vdd/2 ? bg + 0.024 vdd/2 ? bg + 0.04 v ? reflo = bandgap bg ? 0.06 bg bg + 0.06 v ? reflo = 2 x bandgap ? p2[6] (p2[6] = 1.3v) 2 x bg ? p2[6] ? 0.084 2 x bg ? p2[6] + 0.025 2 x bg ? p2[6] + 0.134 v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) p2[4] ? bg ? 0.056 p2[4] ? bg + 0.026 p2[4] ? bg + 0.107 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] ? p2[6] ? 0.057 p2[4] ? p2[6] + 0.026 p2[4] ? p2[6] + 0.110 v table 11-10. 3.3v dc analog reference specifications parameter description min. typ. max. unit bg bandgap voltage reference 1.28 1.30 1.32 v ? agnd = vdd/2 [2] vdd/2 ? 0.03 vdd/2 ? 0.01 vdd/2 + 0.005 v ? agnd = 2 x bandgap [2] not allowed ? agnd = p2[4] (p2[4] = vdd/2) p2[4] ? 0.008 p2[4] + 0.001 p2[4] + 0.009 v ? agnd = bandgap [2] bg ? 0.009 bg + 0.005 bg + 0.015 v ? agnd = 1.6 x bandgap [2] 1.6 x bg ? 0.027 1.6 x bg ? 0.010 1.6 x bg + 0.018 v ? agnd column to column variation (agnd = vdd/2) [2] ?0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap not allowed ? refhi = 3 x bandgap not allowed ? refhi = 2 x bandgap + p2[6] (p2[6] = 0.5v) not allowed ? refhi = p2[4] + bandgap (p2[4] = vdd/2) not allowed ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] + p2[6] ? 0.075 p2[4] + p2[6] ? 0.009 p2[4] + p2[6] + 0.057 v ? refhi = 3.2 x bandgap not allowed ? reflo = vdd/2 ? bandgap not allowed ? reflo = bandgap not allowed ? reflo = 2 x bandgap - p2[6] (p2[6] = 0.5v) not allowed ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) not allowed ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] ? p2[6] ? 0.048 p2[4] ? p2[6] + 0.022 p2[4] ? p2[6] + 0.092 v note: 2. agnd tolerance includes the offsets of the local buffer in the encore iii block. bandgap voltage is 1.3v 0.02v.
cy7c6421 5 document 38-08036 rev. *a page 16 of 26 11.3.6 dc analog encore iii block specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 11.3.7 dc por and lvd specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. note the bits porlev and vm in the table below refer to bits in the vlt_cr register. see the psoc mixed-signal array technical reference manual for more information on the vlt_cr register. table 11-11. dc analog encore iii block specifications parameter description min. typ. max. unit notes r ct resistor unit value (continuous time) ? 12.2 ? k ? c sc capacitor unit value (switched capacitor) ? 80 ? ff table 11-12. dc por and lvd specifications parameter description min. typ. max. unit notes v ppor0r v ppor1r v ppor2r vdd value for ppor trip (positive ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.91 4.39 4.55 ? v v v v ppor0 v ppor1 v ppor2 vdd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.82 4.39 4.55 ? v v v v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98 [3] 3.08 3.20 4.08 4.57 4.74 [4] 4.82 4.91 v v v v v v v v notes: 3. always greater than 50 mv above ppor (porlev = 00) for falling supply. 4. always greater than 50 mv above ppor (porlev = 10) for falling supply.
cy7c6421 5 document 38-08036 rev. *a page 17 of 26 11.3.8 dc programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 11-13. dc programming specifications parameter description min. typ. max. unit notes i ddp supply current during programming or verify ? 15 30 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd ? 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [5] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years note: 5. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information .
cy7c6421 5 document 38-08036 rev. *a page 18 of 26 11.4 ac electrical characteristics 11.4.1 ac chip-level specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 11-14. ac chip-level specifications parameter description min. typ. max. unit notes f imo245v internal main oscillator frequency for 24 mhz (5v) 23.04 24 24.96 [6, 7] mhz trimmed for 5v operation using factory trim values. f imo243v internal main oscillator frequency for 24 mhz (3.3v) 22.08 24 25.92 [6,8] mhz trimmed for 3.3v operation using factory trim values. f imousb internal main oscillator frequency with usb frequency locking enabled and usb traffic present. 23.94 24 24.06 [7] mhz 0 c < t a < 70 c f cpu1 cpu frequency (5v nominal) 0.93 24 24.96 [6,7] mhz f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.96 [7, 8] mhz f blk5 digital psoc block frequency (5v nominal) 0 48 49.92 [6, 7, 9] mhz refer to the ac digital block specifications. f blk3 digital psoc block frequency (3.3v nominal) 0 24 25.92 [7, 9] mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz jitter32k 32-khz period jitter ? 100 ns step24m 24-mhz trim step size ? 50 ? khz fout48m 48-mhz output frequency 46.08 48.0 49.92 [6, 8] mhz trimmed. utilizing factory trim values. jitter24m1 24-mhz period jitter (imo) peak-to-peak ? 300 ps f max maximum frequency of signal on row input or row output. ? ? 12.96 mhz t ramp supply ramp time 0 ? ? s notes: 6. 4.75v < vdd < 5.25v. 7. accuracy derived from internal main oscillator with appropriate trim for vdd range. 8. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for in formation on trimming for operation at 3.3v. 9. see the individual user module data sheets for information on maximum frequencies for user modules. jitter24m1 f 24m figure 11-2. 24 mhz period jitter (imo) timing diagram
cy7c6421 5 document 38-08036 rev. *a page 19 of 26 11.4.2 ac general purpose io specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 11.4.3 ac full-speed usb specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 11-15. ac gpio specifications parameter description min. typ. max. unit notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10%?90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10%?90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10%?90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10%?90% table 11-16. ac full-speed (12 mbps) usb specifications parameter description min. typ. max. unit notes t rfs transition rise time 4 ? 20 ns for 50 pf load. t fss transition fall time 4 ? 20 ns for 50 pf load. t rfmfs rise/fall time matching: (t r /t f )90 ? 111 % for 50 pf load. t dratefs full-speed data rate 12 ? 0.25% 12 12 + 0.25% mbps tfallf tfalls trisef tr is es 90% 10% gpio pin output voltage figure 11-3. gpio timing diagram
cy7c6421 5 document 38-08036 rev. *a page 20 of 26 11.4.4 ac digital block specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 11.4.5 ac external clock specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 11-17. ac digital block specifications function description min. typ. max. unit notes timer capture pulse width 50 [10] ? ? ns maximum frequency, no capture ? ? 49.92 mhz 4.75v < vdd < 5.25v. maximum frequency, with capture ? ? 25.92 mhz counter enable pulse width 50 [10] ? ? ns maximum frequency, no enable input ? ? 49.92 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 25.92 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [10] ? ? ns disable mode 50 [10] ? ? ns maximum frequency ? ? 49.92 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 49.92 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between trans- missions 50 [10] ? ? ns trans- mitter maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking. note: 10. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). table 11-18. ac external clock specifications parameter description min. typ. max. unit notes f oscext frequency for usb applications 23.94 24 24.06 mhz ? duty cycle 47 50 53 % ? power up to imo switch 150 ? ? s
cy7c6421 5 document 38-08036 rev. *a page 21 of 26 11.4.6 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 11-19. 5v ac analog output buffer specifications parameter description min. typ. max. unit notes t rob rising settling time to 0.1%, 1v step, 100-pf load power = low power = high ? ? ? ? 2.5 2.5 s s t sob falling settling time to 0.1%, 1v step, 100-pf load power = low power = high ? ? ? ? 2.2 2.2 s s sr rob rising slew rate (20% to 80%), 1v step, 100-pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100-pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s bw obss small signal bandwidth, 20mv pp , 3-db bw, 100-pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw obls large signal bandwidth, 1v pp , 3-db bw, 100-pf load power = low power = high 300 300 ? ? ? ? khz khz table 11-20. 3.3v ac analog output buffer specifications parameter description min. typ. max. unit notes t rob rising settling time to 0.1%, 1v step, 100-pf load power = low power = high ? ? ? ? 3.8 3.8 s s t sob falling settling time to 0.1%, 1v step, 100-pf load power = low power = high ? ? ? ? 2.6 2.6 s s sr rob rising slew rate (20% to 80%), 1v step, 100-pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100-pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s bw obss small signal bandwidth, 20mv pp , 3db bw, 100-pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw obls large signal bandwidth, 1v pp , 3db bw, 100-pf load power = low power = high 200 200 ? ? ? ? khz khz
cy7c6421 5 document 38-08036 rev. *a page 22 of 26 11.4.7 ac programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 11.4.8 ac i 2 c specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and 0 c < t a < 70 c, or 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 11-21. ac programming specifications parameter description min. typ. max. unit notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 30 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns vdd > 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 < vdd < 3.6 table 11-22. ac characteristics of the i 2 c sda and scl pins for vdd parameter description standard mode fast mode unit notes min. max. min. max. f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 250 ?100 [11] ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns note: 11. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released.
cy7c6421 5 document 38-08036 rev. *a page 23 of 26 figure 11-4. definition for timing for fast/standard mode on the i 2 c bus 12.0 packaging information this section illustrates the package specification for the cy7c64215 encore iii, along with the thermal impedance for the package. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress.com/support/link.cfm?mr=poddim. 12.1 packaging dimensions figure 12-1. 56-lead (8x8 mm) mlf important note for information on the preferred dimensions for mounting mlf packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf. s da scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c
cy7c6421 5 document 38-08036 rev. *a page 24 of 26 12.2 thermal impedance 12.3 solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. figure 12-2. 28-lead shrunk small outline package table 12-1. thermal impedance for the package package typical ja * 56 mlf 20 o c/w 28 ssop 96 o c/w * t j = t a + power x ja 51-85079-*c table 12-2. solder reflow peak temperature package minimum peak temperature* maximum peak temperature 56 mlf 240c 260c 28 ssop 240c 260c *higher temperatures may be required based on the solder melting point. typical temperatures for solder are 2205c with sn- pb or 2455c with sn-ag-cu paste. refer to the solder manufacturer specifications.
cy7c6421 5 document 38-08036 rev. *a page 25 of 26 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress against all charges. 13.0 ordering information . microsoft and windows are registered trademarks of microsoft corporation. purchase of i2c components from cypress or one of its sublicensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. encore, psoc, and programmable system-on-chip are trademarks of cypress semiconductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. table 13-1. cy8c24794 psoc device key features and ordering information package ordering code flash size sram (bytes) 56 pin mlf CY7C64215-56LFXC 16k 1k 28 pin ssop cy7c64215-28pvxc 16k 1k
cy7c6421 5 document 38-08036 rev. *a page 26 of 26 document history page description title: cy7c64215, encore? iii full speed usb controller document number: 38-08036 rev. ecn no. issue date orig. of change description of change ** 131325 see ecn xgr new data sheet *a 385256 see ecn bha changed from advance information to preliminary. added standard data sheet items. changed part number from cy7c642xx to cy7c64215.

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